While digital circuits are ultimately intended to process discrete values—such as “0” and “1,” at the semiconductor device level, such circuits invariably encode discrete signals using physical quantities such as voltage and current. Consequently, when digital signals transition inside or outside a semiconductor device, they cause analog transients in voltage level, current level, or both. As technology advances, this “analog” behavior of digital circuits becomes increasingly relevant to the correct operation of a semiconductor device. For example, if the time it takes for a voltage to transition from a “0”-level to a “1”-level is excessively long, the semiconductor device may cease to operate altogether. Similarly, if a logical “1” (“0”) is encoded using too low (high) a voltage or current, the resulting circuit could fail to operate correctly. Other examples of analog phenomena include timing uncertainty or tolerance to timing uncertainty. As a specific example, consider two semiconductor devices that are expected to communicate with each other over a copper wire. If the timing of the digital signals from the source to the destination is excessively perturbed, the resulting communication link could be corrupted. Apart from the above “behind-the-scenes” analog behavior of digital circuits, it is often necessary to momentarily and deliberately convert digital signals into analog signals for ease of processing and implementation, as would be the case in a wireless communications system.
The evaluation of the analog behavior of circuits is a very important step in the semiconductor industry. Circuits and systems designers always need test and measurement tools to debug, characterize, and production-test their designs. These test and measurement tools can take on several forms. In general, various bench tools are available for signal integrity measurements, such as oscilloscopes (to measure voltage or current or electromagnetic waves in general), jitter analyzers (to measure timing uncertainty), and spectrum analyzers (to measure frequency). Such instruments have historically been well suited to measure the interface portion of a semiconductor device, e.g., the input and output ports. However, entire systems are currently being constructed onto a very small form factor. The current-generation test and measurement technology is not capable of analyzing internal circuitry because of access difficulties. To test is to disturb, so transferring a very low level signal from the micro-scale of a modern device to the macro scale of the test instrument is too disruptive to the signal being measured.
Modern measurement instruments almost invariably rely on powerful digital signal processing (DSP) techniques to facilitate automation and to enhance measurement accuracy and repeatability. Using DSP techniques, a device-under-test (DUT) response signal is measured by first digitizing it using an accurate analog-to-digital (A/D) converter. Subsequently, microprocessor-based computations are performed in order to analyze the digitized signals. For example, hardware or software implementations of a Fast Fourier Transform (FFT) are utilized before displaying the results to a user monitor.
The digitization step involves a clocking circuit, often called a “time-base generator” in oscilloscope terminology, in addition to the A/D converter. In general, the clocking circuit is the most important and most challenging component in an instrument such as an oscilloscope or a jitter analyzer in terms of design and implementation. Referring to FIGS. 1A and 1B, which illustrate the digitization of an analog waveform 10, the clocking circuit defines a horizontal (time) axis 12 against which signal parameters of the waveform are traced and measured. The more accurate the signal parameters can be traced along horizontal axis 12, the more accurate the overall measurement. Accuracy is increased by increasing the frequency of the sampling clock signal 14 output by the clocking circuit to a conventional A/D converter 16. Much of the clocking challenges occur when the signal frequency is faster than half of the clocking circuit frequency. Under this condition, conventional A/D converter 16 output exhibits aliasing and measurements become erroneous. Unfortunately, most measurement applications fall into this category. A lot of advancement has to be made in the area of clocking and digitization for digitizing high-frequency signals.
Still referring to FIGS. 1A and 1B, all modern digitization techniques generally revolve around placing the sampling instants of A/D converter 16 as close to each other as possible. Real-time oscilloscopes literally create multiple delayed replicas of a single “slow” clock signal and use each of the replicas to clock a separate A/D converter. This is illustrated in the time-interleaved A/D converter architecture 20 of FIG. 2. If 16 copies of a clock signal 22 are created and each is delayed by 1/16th of the period with respect to the other, then an effective digitization frequency that is 16 times faster than the slow clock can be achieved. All that needs to be done is to combine the outputs of all 16 A/D converters 24 to create an aggregate digitized waveform. An example of such implementation is the Agilent 54855A digital sampling oscilloscope, available from Agilent Technologies, Santa Clara, Calif. Such implementation is extremely costly, requires rather large implementation area, and involves significant calibration procedures. These limitations make this technology generally suitable only for single-channel high-end equipment such as wide-bandwidth oscilloscopes. For obvious reasons it is not suited for integration as a signal-integrity measurement macro within a semiconductor device.
Alternatively, equivalent-time or sub-sampling instruments are constructed that relax the clock circuit frequency requirements significantly. In such instruments, the requirement to digitize signals in real-time is relaxed. Instead of creating multiple delayed copies of a clock, one sub-sampling approach takes multiple conversion passes to digitize a repetitive signal using a single clock signal. The repetitive signal can have a bandwidth that is much higher than the single clock signal used for digitization. First, the “slow” clock is used with a zero phase delay to sample the first input test period. The clock is then incremented by Δts seconds on each subsequent run of the repetitive signal under test until the sampling clock has been delayed by the equivalent of one period. A total phase shift of approximately one period ensures that complete coverage of the input waveform is obtained with a timing resolution of Δts seconds, although such complete coverage is not always necessary in many applications. FIG. 3 provides a graphical representation 30 of this sub-sampling algorithm (UTP in FIG. 3 means “unit test period”). A possible hardware implementation 40 is illustrated simplistically in FIG. 4, and it involves a delay chain 42 that can generate accurate phase delays and a multiplexer 44 for selecting the appropriate phase-delayed clocks (not shown).
Both methods described above have serious limitations associated with the reliable generation of small delay increments and with accumulated jitter in any circuitry that generates such delay increments. The impact of unwanted jitter on A/D-converter performance can be severe, and in the case of test and measurement applications, jitter is often the very phenomenon being measured. More importantly, delay-line resolution in most available semiconductor technologies is often 10 to 100 times more than what is required from a measurement instrument. In jitter measurement for example, one often needs delay increments of 1 psec or even 100 fsec, whereas delay line resolution in the best of cases is limited to about 50 psec. To combat this limitation, some sub-sampling architectures employ even more hardware to enhance the delay line resolution. Consider, for example, the vernier delay line circuitry 50 of FIG. 5. Instead of delaying just the sampling clock signal 52 of the A/D converter 54, the input signal 56 being measured is itself delayed, albeit by a slightly different amount. By controlling the delay of input signal 56 with respect to the delay of clock signal 52, effective resolution that is less than the absolute minimum delay of each of the individual delay lines can be achieved. This concept is referred to as a “vernier delay line.” Apart from the obvious increase in implementation area, it is extremely difficult to match the delay values of both vernier delay lines. No published results have demonstrated less than about 20 psec delay resolution.
As an alternative to vernier delay lines, offset frequency sampling can be employed. A fractional frequency divider is used to clock the A/D converter at a rate 1/(T+ΔT) that is slightly offset from the repetition rate, 1/T, of the signal being measured. Sampling the input signal with such a clock ensures that one point per input signal period is sampled and that the sample point moves Δt seconds relative to the previous sampling instant on the next run of the input signal. A high sampling resolution, 1/Δt, can be achieved using this method, but this requires a high accuracy frequency synthesizer. Indeed commercial implementations of this technique involve a significantly more elaborate scheme than what has just been described. For some applications such as built-in test, such as disclosed in U.S. Pat. No. 7,158,899, these elaborate schemes cannot be employed, thus rendering the performance of the resulting solution very questionable. Effectively, the scheme of the '899 patent relies on two free-running oscillators that will undoubtedly wander significantly with respect to each other. Controlling the wander or filtering it out in a post-processing step is extremely challenging.
Other innovative equivalent-time technologies are similarly employed in high-performance oscilloscopes, such as disclosed in U.S. Pat. No. 6,650,101, and they all attempt to achieve the same goal of creating the perfect time-base. Similarly, in the context of jitter measurement applications, other measurement techniques exist, such as the techniques disclosed in U.S. Pat. No. 6,449,570, but they again all revolve around translating very small time increments into more manageable time delays.